The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to methods of fabricating structures that include contacts coupled with a source/drain region of a field-effect transistor and related structures.
As circuit sizes have continued to shrink, modifications to processes for fabricating active devices of an integrated circuit become necessary to ensure proper functioning of the circuit and devices and prevent issues such as electrical shorts. Fabrication techniques that work for making integrated circuits with larger feature sizes may break down for smaller feature sizes, requiring new processes to be developed to replace outdated methods. For example, in many fabrication processes an interlayer dielectric is formed ahead of trench silicidation processes to form conductive contacts between metal layers and active devices; portions of the interlayer dielectric remain as pillars while other portions are removed to allow for formation of conductive contacts. However, some sacrificial interlayer dielectric materials, such as amorphous silicon, will end up with “voids” formed during deposition of the material, and these voids can trap other dielectric materials in successive fabrication steps that can partially or entirely prevent removal of the interlayer dielectric, resulting in poor conductive contact structures. Other interlayer dielectric materials are difficult to remove because the etchants used to remove the materials cannot achieve perfect selectivity to the interlayer dielectric material, and may partially remove other portions of the circuit structure that must remain intact; other etchants that can achieve such high selectivity may no longer be usable with smaller feature sizes.